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Single-Event Tolerant Flip-Flop Design in 40-nm Bulk CMOS Technology

✍ Scribed by Jagannathan, S.; Loveless, T. D.; Bhuva, B. L.; Wen, S.-J.; Wong, R.; Sachdev, M.; Rennie, D.; Massengill, L. W.

No coin nor oath required. For personal study only.

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