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Impact of Circuit Placement on Single Event Transients in 65 nm Bulk CMOS Technology

✍ Scribed by He Yibai, ; Chen Shuming, ; Chen Jianjun, ; Chi Yaqing, ; Liang Bin, ; Liu Biwei, ; Qin Junrui, ; Du Yankang, ; Huang Pengcheng,

No coin nor oath required. For personal study only.

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