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The Effect of Layout Topology on Single-Event Transient Pulse Quenching in a 65 nm Bulk CMOS Process

✍ Scribed by Ahlbin, J. R.; Gadlage, M. J.; Ball, D. R.; Witulski, A. W.; Bhuva, B. L.; Reed, R. A.; Vizkelethy, G.; Massengill, L. W.

No coin nor oath required. For personal study only.

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