Modeling and testing for stuck faults in BiCMOS combinational circuits

✍ Scribed by Asad A. Ismaeel; Rakesh Bhatnagar

• Publisher: Elsevier Science
• Year: 1997
• Tongue: English
• Weight: 968 KB
• Volume: 28
• Category: Article
• ISSN: 0026-2692
• DOI: 10.1016/s0026-2692(97)00008-6

✦ Synopsis

A transistor level model and a testing methodology are presented for BiCMOS circuits. The model fully describes the functional (logical) grad parametric behavior of the 13iCMOS circuits in the presence of transistor stuck faults. Tile model employs the logic transistor function (LTF). The LTF describes the circuit in terms of its input variables and transistor topology. The model assumes tbur logic values: 0, 1, M and I, where M and I imply a memory" and an indeterminate element, respectively. The faults m BiCMOS circuits may affect the logic level at the output or the parameters of the circuit. The circuits arc nonnally tested at the parametric level by IDDQ (steady state power supply current) testing or by timing testing. The LTF model is utilized to generate the test vectors for both the functional testing and the parametric testing. Simulation is performed using hspice to support the results.