𝔖 Bobbio Scriptorium
✦   LIBER   ✦

A method of diagnosing single stuck-at faults in combinational circuits

✍ Scribed by Teruhiko Yamada; Yoshiyuki Nakamura

Publisher
John Wiley and Sons
Year
1992
Tongue
English
Weight
618 KB
Volume
23
Category
Article
ISSN
0882-1666

No coin nor oath required. For personal study only.

✦ Synopsis

Abstract

A new method is proposed to diagnose single stuck‐at faults in combinational circuits. In this method, based on the operations of the nonfaulty circuit, first the possible faulty paths are examined from the primary outputs, at which errors have been observed, toward the primary inputs to narrow down the suspected faulty section. Then a fault simulation is conducted to deduce the fault location. According to the computational experiments it is expected that this method is faster than the conventional fault dictionary methods by about two orders of magnitude and the diagnosis time is almost proportional to the circuit size. Thus, this method is very effective for fault diagnosis of large‐scale circuits.

πŸ“œ SIMILAR VOLUMES

Diagnostic simulation of stuck-at faults
Diagnostic simulation of stuck-at faults in combinational circuits
✍ Sreejit Chakravarty; Yiming Gong; Srikanth Venkataraman πŸ“‚ Article πŸ“… 1996 πŸ› Springer US 🌐 English βš– 769 KB

Two faults are said to be equivalent, with respect to a test set T, iff they cannot be distinguished by any test in T. The sizes of the corresponding equivalence classes of faults are used as a basis for comparing the diagnostic capability of two given test sets. A novel algorithm, called "multiway

Modeling and testing for stuck faults in
Modeling and testing for stuck faults in BiCMOS combinational circuits
✍ Asad A. Ismaeel; Rakesh Bhatnagar πŸ“‚ Article πŸ“… 1997 πŸ› Elsevier Science 🌐 English βš– 968 KB

A transistor level model and a testing methodology are presented for BiCMOS circuits. The model fully describes the functional (logical) grad parametric behavior of the 13iCMOS circuits in the presence of transistor stuck faults. Tile model employs the logic transistor function (LTF). The LTF descri