Stuck-open faults test generation for cmos combinational circuits
โ Scribed by Seiji Kajihara; Noriyoshi Itazaki; Kozo Kinoshita
- Publisher
- John Wiley and Sons
- Year
- 1991
- Tongue
- English
- Weight
- 716 KB
- Volume
- 22
- Category
- Article
- ISSN
- 0882-1666
No coin nor oath required. For personal study only.
๐ SIMILAR VOLUMES
A transistor level model and a testing methodology are presented for BiCMOS circuits. The model fully describes the functional (logical) grad parametric behavior of the 13iCMOS circuits in the presence of transistor stuck faults. Tile model employs the logic transistor function (LTF). The LTF descri
A new algorithm to generate test sets for stuck-at faults in combinational logic circuits via fault simulation is presented. The algorithm is non-path-sensitizing, non-pathtracing and can be easily implemented on a computer. The stuck-at fault model in the algorithm is developed using the component