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An algorithm to generate complete test sets for stuck-at faults in combinational logic circuits

✍ Scribed by Leonard J. Tung; David V. Kerns

Publisher: Elsevier Science
Year: 1988
Tongue: English
Weight: 581 KB
Volume: 325
Category: Article
ISSN: 0016-0032
DOI: 10.1016/0016-0032(88)90051-8

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✦ Synopsis

A new algorithm to generate test sets for stuck-at faults in combinational logic circuits via fault simulation is presented. The algorithm is non-path-sensitizing, non-pathtracing and can be easily implemented on a computer. The stuck-at fault model in the algorithm is developed using the component connection model. The algorithm can be extended to sequential digital circuits. The software generates the complete set of test input vectors,for each single stuck-at fault.

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✍ Leonard J. Tung 📂 Article 📅 1989 🏛 Elsevier Science 🌐 English ⚖ 726 KB

An algorithm for stuck-at fault coverage analysis of digital logic circuits is presented. Based on a recently developed stuck-at fault model, the algorithm determines the effectiveness of a given test input set. The algorithm is applicable for studying sequential logic circuits, as well as combinati