✦ LIBER ✦

An algorithm for stuck-at fault coverage analysis of combinational and sequential logic circuits

✍ Scribed by Leonard J. Tung

Publisher: Elsevier Science
Year: 1989
Tongue: English
Weight: 726 KB
Volume: 326
Category: Article
ISSN: 0016-0032
DOI: 10.1016/0016-0032(89)90070-7

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✦ Synopsis

An algorithm for stuck-at fault coverage analysis of digital logic circuits is presented. Based on a recently developed stuck-at fault model, the algorithm determines the effectiveness of a given test input set. The algorithm is applicable for studying sequential logic circuits, as well as combinational logic circuits. The software developed forfault coverage analysis of all single stuck-at faults is simple and fast.

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An algorithm to generate complete test sets for stuck-at faults in combinational logic circuits

✍ Leonard J. Tung; David V. Kerns 📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 581 KB

A new algorithm to generate test sets for stuck-at faults in combinational logic circuits via fault simulation is presented. The algorithm is non-path-sensitizing, non-pathtracing and can be easily implemented on a computer. The stuck-at fault model in the algorithm is developed using the component