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[IEEE IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004. - San Francisco, CA, USA (Dec. 13-15, 2004)] IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004. - A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

✍ Scribed by Bai, P.; Auth, C.; Balakrishnan, S.; Bost, M.; Brain, R.; Chikarmane, V.; Heussner, R.; Hussein, M.; Hwang, J.; Ingerly, D.; James, R.; Jeong, J.; Kenyon, C.; Lee, E.; Lee, S.-H.; Lindert, N.; Liu, M.; Ma, Z.; Marieb, T.; Murthy, A.; Nagisetty, R.; Natarajan, S.; Neirynck, J.; Ott, A.; Parker, C.; Sebastian, J.; Shaheed, R.; Sivakumar, S.; Steigerwald, J.; Tyagi, S.; Weber, C.; Woolery, B.; Yeoh, A.; Zhang, K.; Bohr, M.

Book ID: 121444099
Publisher: IEEE
Year: 2004
Tongue: English
Weight: 253 KB
Category: Article
ISBN-13: 9780780386846
DOI: 10.1109/IEDM.2004.1419253

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