𝔖 Bobbio Scriptorium

✦ LIBER ✦

[IEEE Comput. Soc 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Monterey, CA, USA (3-5 Oct. 2005)] 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) - Multiple transient faults in logic: an issue for next generation ICs?

✍ Scribed by Rossi, D.; Omana, M.; Toma, F.; Metra, C.

Book ID: 115525584
Publisher: IEEE Comput. Soc
Year: 2005
Weight: 285 KB
Volume: 0
Category: Article
ISBN-13: 9780769524641
DOI: 10.1109/dftvs.2005.47

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

[IEEE Comput. Soc 20th IEEE Internationa

[IEEE Comput. Soc 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Monterey, CA, USA (3-5 Oct. 2005)] 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) - Computing cache vulnerability to transient errors and its implication

✍ Wei Zhang, 📂 Article 📅 2005 🏛 IEEE Comput. Soc ⚖ 236 KB

[IEEE Comput. Soc 20th IEEE Internationa

[IEEE Comput. Soc 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Monterey, CA, USA (3-5 Oct. 2005)] 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) - Soft error modeling and protection for sequential elements

✍ Asadi, H.; Tahoori, M.B. 📂 Article 📅 2005 🏛 IEEE Comput. Soc ⚖ 258 KB

[IEEE Comput. Soc 20th IEEE Internationa

[IEEE Comput. Soc 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Monterey, CA, USA (3-5 Oct. 2005)] 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05) - Concurrent error detection of polynomial basis multiplication over extension fields using a multiple-bit parity scheme

✍ Bayat-Sarmadi, S.; Hasan, M.A. 📂 Article 📅 2005 🏛 IEEE Comput. Soc ⚖ 312 KB

[IEEE Comput. Soc 1997 IEEE Internationa

[IEEE Comput. Soc 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Paris, France (20-22 Oct. 1997)] 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Multiple fault detection in logic resources of FPGAs

✍ Wei Liang Huang, ; Meyer, F.J.; Lombardi, F. 📂 Article 📅 1997 🏛 IEEE Comput. Soc ⚖ 523 KB

[IEEE Comput. Soc 17th IEEE Internationa

[IEEE Comput. Soc 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. DFT 2002 - Vancouver, BC, Canada (6-8 Nov. 2002)] 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings. - Fault-tolerant CAM architectures: a design framework

✍ Salice, F.; Sami, M.G.; Stefanelli, R. 📂 Article 📅 2002 🏛 IEEE Comput. Soc 🌐 English ⚖ 426 KB

[IEEE 2009 24th IEEE International Sympo

[IEEE 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT) - Chicago, Illinois, USA (2009.10.7-2009.10.9)] 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Reliability and Performance Analysis of FPGA-Based Fault Tolerant System

✍ Noji, Ryoji; Fujie, Satoshi; Yoshikawa, Yuki; Ichihara, Hideyuki; Inoue, Tomoo 📂 Article 📅 2009 🏛 IEEE ⚖ 683 KB