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[IEEE 2008 Symposium on VLSI Technology - Honolulu, HI, USA (2008.06.17-2008.06.19)] 2008 Symposium on VLSI Technology - 45nm low-power CMOS SoC technology with aggressive reduction of random variation for SRAM and analog transistors

✍ Scribed by Ekbote, S.; Benaissa, K.; Obradovic, B.; Liu, S.; Shichijo, H.; Hou, F.; Blythe, T.; Houston, T. W.; Martin, S.; Taylor, R.; Singh, A.; Yang, H.; Baldwin, G.

Book ID: 126755026
Publisher: IEEE
Year: 2008
Weight: 336 KB
Category: Article
ISBN: 142441802X
DOI: 10.1109/VLSIT.2008.4588602

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