[IEEE 2008 Symposium on VLSI Technology - Honolulu, HI, USA (2008.06.17-2008.06.19)] 2008 Symposium on VLSI Technology - A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

✍ Scribed by Chen, X.; Samavedam, S.; Narayanan, V.; Stein, K.; Hobbs, C.; Baiocco, C.; Li, W.; Jaeger, D.; Zaleski, M.; Yang, H. S.; Kim, N.; Lee, Y.; Zhang, D.; Kang, L.; Chen, J.; Zhuang, H.; Sheikh, A.; Wallner, J.; Aquilino, M.; Han, J.; Jin, Z.; Li, J.; Massey, G.; Kalpat, S.; Jha, R.; Moumen, N.; Mo, R.; Kirshnan, S.; Wang, X.; Chudzik, M.; Chowdhury, M.; Nair, D.; Reddy, C.; Teh, Y. W.; Kothandaraman, C.; Coolbaugh, D.; Pandey, S.; Tekleab, D.; Thean, A.; Sherony, M.; Lage, C.; Sudijono, J.; Lindsay, R.; Ku, J. H.; Khare, M.; Steegen, A.

• Book ID: 120814459
• Publisher: IEEE
• Year: 2008
• Weight: 519 KB
• Category: Article
• ISBN: 142441802X
• DOI: 10.1109/VLSIT.2008.4588573