𝔖 Bobbio Scriptorium
✦   LIBER   ✦

Design Guidelines for the Noise Optimization of a 0.18 μm CMOS Low-Noise Amplifier

✍ Scribed by Ahmed A. Youssef

Publisher
Springer
Year
2006
Tongue
English
Weight
297 KB
Volume
46
Category
Article
ISSN
0925-1030

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Ka-band 0.18 μm CMOS low noise amplifier
Ka-band 0.18 μm CMOS low noise amplifier with 5.2 dB noise figure
✍ Win-Ming Chang; Zi-Hao Hsiung; Christina F. Jou 📂 Article 📅 2007 🏛 John Wiley and Sons 🌐 English ⚖ 220 KB

## Abstract A Ka‐band low noise amplifier (LNA) using three cascaded stages was designed and implemented in a standard 0.18 μm CMOS technology. The fabricated Ka‐band LNA achieves power gain (S21) above 12 dB from 30 to 32 GHz and a minimal noise figure of 5.2 dB at 31.5 GHz. The three cascaded sta

A miniature low-power ultra-wideband low
A miniature low-power ultra-wideband low noise amplifier in 0.18 μm CMOS
✍ Xin Guan; Cam Nguyen 📂 Article 📅 2011 🏛 John Wiley and Sons 🌐 English ⚖ 515 KB

A 0.18-lm CMOS low-noise amplifier (LNA) operating over the entire ultrawideband (UWB) frequency range of 3.1-10.6 GHz, has been designed, fabricated, and tested. The UWB LNA achieves the measured power gain of 7.5 6 2.5 dB, minimum input matching of À8 dB, noise figure from 3.9 to 6.3 dB, and IIP3

A low power 20-GHz low-noise amplifier f
A low power 20-GHz low-noise amplifier fabricated using 0.18-μm CMOS technology
✍ J.-X. Liu; H.-C. Kuo; Y.-K. Chu; J.-F. Yeh; H.-R. Chuang 📂 Article 📅 2009 🏛 John Wiley and Sons 🌐 English ⚖ 536 KB

## Abstract A 20‐GHz CMOS low‐noise amplifier (LNA) fabricated with the 0.18 μm process is presented. This two‐stage cascaded common source LNA exhibits low power consumption with a satisfying performance such as overall gain and noise figure (NF). The measurement is performed on‐wafer. The 20‐GHz

23-GHz low-noise amplifier using paralle
23-GHz low-noise amplifier using parallel feedback in 0.18-μm CMOS
✍ B. M. Frank; M. M. Hossain; Y. M. M. Antar 📂 Article 📅 2005 🏛 John Wiley and Sons 🌐 English ⚖ 120 KB

## Abstract A three‐stage low‐noise amplifier (LNA) fabricated in a standard 0.18‐μm CMOS process (__f__~__T__~ = 45 GHz) with a maximum gain of 18 dB at 23.2 GHz and a 5.8‐dB noise figure is presented. Parallel feedback between the gate and drain is used in all three stages. This configuration als

A 30-GHz 10-dB low noise amplifier using
A 30-GHz 10-dB low noise amplifier using standard 0.18-μm CMOS technology
✍ Hsin-Lung Tu; Tsung-Yu Yang; Kung-Hao Liang; Hwann-Kaeo Chiou 📂 Article 📅 2007 🏛 John Wiley and Sons 🌐 English ⚖ 192 KB

## Abstract A three‐stage 30‐GHz low noise amplifier (LNA) was designed and fabricated in a standard 0.18‐μm CMOS technology. The LNA has demonstrated a 10‐dB gain and a minimum noise figure of 5.2 dB at 30 GHz. The achieved input 1‐dB compression point (IP~1 dB~) and third order intercept point (I

A K-band low-noise amplifier in 0.18-μm
A K-band low-noise amplifier in 0.18-μm CMOS technology for SUB-1-V operation
✍ Jun-De Jin; Shawn S. H. Hsu 📂 Article 📅 2009 🏛 John Wiley and Sons 🌐 English ⚖ 174 KB

## Abstract A K‐band low‐noise amplifier (LNA) was realized in a standard 0.18‐μm CMOS technology. The cascaded common‐source configuration of four stages was adopted for low voltage operation and high gain performance. In addition, the gate‐source transformer feedback technique was employed to ach