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23-GHz low-noise amplifier using parallel feedback in 0.18-μm CMOS

✍ Scribed by B. M. Frank; M. M. Hossain; Y. M. M. Antar

Publisher
John Wiley and Sons
Year
2005
Tongue
English
Weight
120 KB
Volume
45
Category
Article
ISSN
0895-2477

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✦ Synopsis

Abstract

A three‐stage low‐noise amplifier (LNA) fabricated in a standard 0.18‐μm CMOS process (f~T~ = 45 GHz) with a maximum gain of 18 dB at 23.2 GHz and a 5.8‐dB noise figure is presented. Parallel feedback between the gate and drain is used in all three stages. This configuration also provides much better linearity than other LNAs presented by resonating out the effect of C~gd~. The amplifier has an output‐referred 3^rd^‐order intercept of 10 dBm, and a 3‐dB bandwidth of approximately 1 GHz. This paper demonstrates that parallel feedback is a viable technique for the design of 20+‐GHz CMOS LNAs. © 2005 Wiley Periodicals, Inc. Microwave Opt Technol Lett 45: 309–312, 2005; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.20806

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