## Abstract A three‐stage 30‐GHz low noise amplifier (LNA) was designed and fabricated in a standard 0.18‐μm CMOS technology. The LNA has demonstrated a 10‐dB gain and a minimum noise figure of 5.2 dB at 30 GHz. The achieved input 1‐dB compression point (IP~1 dB~) and third order intercept point (I
A low power 20-GHz low-noise amplifier fabricated using 0.18-μm CMOS technology
✍ Scribed by J.-X. Liu; H.-C. Kuo; Y.-K. Chu; J.-F. Yeh; H.-R. Chuang
- Publisher
- John Wiley and Sons
- Year
- 2009
- Tongue
- English
- Weight
- 536 KB
- Volume
- 51
- Category
- Article
- ISSN
- 0895-2477
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✦ Synopsis
Abstract
A 20‐GHz CMOS low‐noise amplifier (LNA) fabricated with the 0.18 μm process is presented. This two‐stage cascaded common source LNA exhibits low power consumption with a satisfying performance such as overall gain and noise figure (NF). The measurement is performed on‐wafer. The 20‐GHz LNA has demonstrated a 9.3 dB gain, a 4.4 dB NF, a −10 dBm input P~1dB~, and a 0.65 dBm IIP3. The power consumption is 9.6 mW from a 1.2 V power supply. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 423–426, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24098
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