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An Algorithm for the Generation of Test Sets for Combinational Logic Networks

โœ Scribed by Wang, D.T.

Book ID
114588350
Publisher
IEEE
Year
1975
Tongue
English
Weight
976 KB
Volume
C-24
Category
Article
ISSN
0018-9340

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A new algorithm to generate test sets for stuck-at faults in combinational logic circuits via fault simulation is presented. The algorithm is non-path-sensitizing, non-pathtracing and can be easily implemented on a computer. The stuck-at fault model in the algorithm is developed using the component