A new algorithm to generate test sets for stuck-at faults in combinational logic circuits via fault simulation is presented. The algorithm is non-path-sensitizing, non-pathtracing and can be easily implemented on a computer. The stuck-at fault model in the algorithm is developed using the component
✦ LIBER ✦
Algorithm for generating tests for detecting faults of type ∼ of logical elements in combinational circuits
✍ Scribed by V. V. Brovarnik; V. A. Pepelyaev
- Publisher
- Springer US
- Year
- 1976
- Tongue
- English
- Weight
- 414 KB
- Volume
- 11
- Category
- Article
- ISSN
- 1573-8337
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