𝔖 Bobbio Scriptorium
✦   LIBER   ✦

A low-voltage low-power programmable fractional PLL in 0.18-μm CMOS process

✍ Scribed by M. Zhang; M. R. Haider; S. K. Islam; R. Vijayaraghavan; A. B. Islam

Publisher
Springer
Year
2010
Tongue
English
Weight
940 KB
Volume
65
Category
Article
ISSN
0925-1030

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

A 5.2-GHz low-power VCO in 0.18-μm CMOS
A 5.2-GHz low-power VCO in 0.18-μm CMOS process
✍ Sheng-Lyang Jang; Kuan-Chun Shen; Cheng-Chen Liu 📂 Article 📅 2009 🏛 John Wiley and Sons 🌐 English ⚖ 349 KB

## Abstract A 5.2 GHz, 0.43 V voltage‐controlled oscillator (VCO) is designed and implemented in a 0.18 μm CMOS 1P6M process. The designed circuit topology consists of two parallel LC resonators in series with the gates of negative differential resistance transistors. At the supply voltage of 0.43

A miniature low-power ultra-wideband low
A miniature low-power ultra-wideband low noise amplifier in 0.18 μm CMOS
✍ Xin Guan; Cam Nguyen 📂 Article 📅 2011 🏛 John Wiley and Sons 🌐 English ⚖ 515 KB

A 0.18-lm CMOS low-noise amplifier (LNA) operating over the entire ultrawideband (UWB) frequency range of 3.1-10.6 GHz, has been designed, fabricated, and tested. The UWB LNA achieves the measured power gain of 7.5 6 2.5 dB, minimum input matching of À8 dB, noise figure from 3.9 to 6.3 dB, and IIP3

A 0.6-V low-power armstrong VCO in 0.18
A 0.6-V low-power armstrong VCO in 0.18 μm CMOS
✍ Cheng-Chen Liu; Sheng-Lyang Jang; Jhao-Jhang Chen; Miin-Horng Juang 📂 Article 📅 2009 🏛 John Wiley and Sons 🌐 English ⚖ 303 KB

## Abstract A low‐power differential voltage‐controlled oscillator (VCO) is proposed and implemented in a 0.18 μm CMOS 1P6M process. It consists of two single‐ended Armstrong oscillators via cross‐coupled transistors to obtain a differential output. At the supply voltage of 0.6 V, the output phase

A low power 20-GHz low-noise amplifier f
A low power 20-GHz low-noise amplifier fabricated using 0.18-μm CMOS technology
✍ J.-X. Liu; H.-C. Kuo; Y.-K. Chu; J.-F. Yeh; H.-R. Chuang 📂 Article 📅 2009 🏛 John Wiley and Sons 🌐 English ⚖ 536 KB

## Abstract A 20‐GHz CMOS low‐noise amplifier (LNA) fabricated with the 0.18 μm process is presented. This two‐stage cascaded common source LNA exhibits low power consumption with a satisfying performance such as overall gain and noise figure (NF). The measurement is performed on‐wafer. The 20‐GHz

Low power concurrent compact dual-band r
Low power concurrent compact dual-band receiver front-end using 0.18-μm CMOS process
✍ Kuo-Hua Cheng 📂 Article 📅 2009 🏛 John Wiley and Sons 🌐 English ⚖ 291 KB

## Abstract A fully monolithic dual‐band concurrent receiver front‐end chip for IEEE 802.11a/b/g applications is presented using 0.18‐μm CMOS 1P6M technology. This dual‐band receiver front‐end design uses sub‐harmonic mixer and only one multi‐modulus synthesizer. This low IF circuit design has the

A low voltage highly linear 24-GHz down
A low voltage highly linear 24-GHz down conversion mixer in 0.18-μm CMOS
✍ Masum Hossain; Brian M. Frank; Yahia M. Antar 📂 Article 📅 2007 🏛 John Wiley and Sons 🌐 English ⚖ 353 KB

## Abstract A K‐band low voltage, highly linear folded Gilbert cell mixer in 0.18‐μm CMOS is presented. An optimization technique been introduced which is particularly applicable to Gilbert cell type mixers. This technique has been experimentally verified with a down conversion mixer fabricated in