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Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits

โœ Scribed by Pomeranz, Irith; Reddy, Sudhakar M.


Book ID
120617767
Publisher
Association for Computing Machinery
Year
2009
Tongue
English
Weight
158 KB
Volume
15
Category
Article
ISSN
1084-4309

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โœ Leonard J. Tung; David V. Kerns ๐Ÿ“‚ Article ๐Ÿ“… 1988 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 581 KB

A new algorithm to generate test sets for stuck-at faults in combinational logic circuits via fault simulation is presented. The algorithm is non-path-sensitizing, non-pathtracing and can be easily implemented on a computer. The stuck-at fault model in the algorithm is developed using the component