Design-for-testability to achieve comple
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Irith Pomeranz; Sudhakar M. Reddy
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Article
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2001
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Elsevier Science
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English
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We propose a testability enhancement technique for delay faults in standard scan circuits that does not involve modiยฎcations to the scan chain. Extra logic is placed on next-state variables, and if necessary, on primary inputs, and can be resynthesized with the circuit to minimize its hardware and p