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Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits

โœ Scribed by Pomeranz, I.; Reddy, S.M.


Book ID
118271247
Publisher
IEEE
Year
2011
Tongue
English
Weight
245 KB
Volume
19
Category
Article
ISSN
1063-8210

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โœ Irith Pomeranz; Sudhakar M. Reddy ๐Ÿ“‚ Article ๐Ÿ“… 2001 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 207 KB

We propose a testability enhancement technique for delay faults in standard scan circuits that does not involve modiยฎcations to the scan chain. Extra logic is placed on next-state variables, and if necessary, on primary inputs, and can be resynthesized with the circuit to minimize its hardware and p