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Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools

✍ Scribed by M. Psarakis; D. Gizopoulos; A. Paschalis

Book ID
110263504
Publisher
Springer US
Year
1998
Tongue
English
Weight
48 KB
Volume
13
Category
Article
ISSN
0923-8174

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A transistor level model and a testing methodology are presented for BiCMOS circuits. The model fully describes the functional (logical) grad parametric behavior of the 13iCMOS circuits in the presence of transistor stuck faults. Tile model employs the logic transistor function (LTF). The LTF descri