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Fault Models and Test Generation for OpAmp Circuits—The FFM

✍ Scribed by José Vicente Calvano; Antônio Carneiro de Mesquita Filho; Vladimir Castro Alves; Marcelo Soares Lubaszewski


Book ID
110298077
Publisher
Springer US
Year
2001
Tongue
English
Weight
296 KB
Volume
17
Category
Article
ISSN
0923-8174

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A transistor level model and a testing methodology are presented for BiCMOS circuits. The model fully describes the functional (logical) grad parametric behavior of the 13iCMOS circuits in the presence of transistor stuck faults. Tile model employs the logic transistor function (LTF). The LTF descri