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On the modelling of digital circuits for the test pattern generation for device input faults

✍ Scribed by Stavros P. Dokouzyannis

Publisher: Elsevier Science
Year: 1994
Tongue: English
Weight: 518 KB
Volume: 34
Category: Article
ISSN: 0026-2714
DOI: 10.1016/0026-2714(94)90287-9

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