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Stress analysis of Si1−xGex embedded source/drain junctions

✍ Scribed by M. Bargallo Gonzalez; E. Simoen; N. Naka; Y. Okuno; G. Eneman; A. Hikavyy; P. Verheyen; R. Loo; C. Claeys; V. Machkaoutsan; P. Tomasini; S.G. Thomas; J.P. Lu; R. Wise

Book ID
103846659
Publisher
Elsevier Science
Year
2008
Tongue
English
Weight
974 KB
Volume
11
Category
Article
ISSN
1369-8001

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✦ Synopsis

The purpose of this paper is to evaluate the impact of the geometry of embedded Si 1Àx Ge x source/drain junctions on the stress field. Stress simulations were performed using TSUPREM4 2D software to further investigate the elastic strain relaxation as a function of Si 1Àx Ge x alloy active size, in the regime where no plastic relaxation is present. Moreover, the role of the epilayer thickness and the Ge content on the stress levels is also discussed. The work is complemented with experimental Raman spectroscopy.

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A new source/drain formation concept based on selective Si etching followed by selective regrowth of in situ B-doped Si 1Àx Ge x is presented. Both process steps are performed in the same reactor to preserve the gate oxide. Well-behaved transistors are demonstrated with a negligibly low gate-to-subs