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Post-layout timing simulation of CMOS circuits

✍ Scribed by Deschacht, D.; Robert, M.; Azemard-Crestani, N.; Auvergne, D.

Book ID: 119777693
Publisher: IEEE
Year: 1993
Tongue: English
Weight: 736 KB
Volume: 12
Category: Article
ISSN: 0278-0070
DOI: 10.1109/43.238609

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