✦ LIBER ✦

CMOS circuit verification with symbolic switch-level timing simulation

✍ Scribed by McDonald, C.B.; Bryant, R.E.

Book ID: 119778759
Publisher: IEEE
Year: 2001
Tongue: English
Weight: 330 KB
Volume: 20
Category: Article
ISSN: 0278-0070
DOI: 10.1109/43.913762

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Formal verification of memory circuits b

Formal verification of memory circuits by switch-level simulation

✍ Bryant, R.E. 📂 Article 📅 1991 🏛 IEEE 🌐 English ⚖ 988 KB

Switch-level simulation of total dose ef

Switch-level simulation of total dose effects on CMOS VLSI circuits

✍ Bhuva, B.L.; Paulos, J.J.; Gyurcsik, R.S.; Kerns, S.E. 📂 Article 📅 1989 🏛 IEEE 🌐 English ⚖ 613 KB

Switching activity evaluation of CMOS di

Switching activity evaluation of CMOS digital circuits using logic timing simulation

✍ Juan-Chico, J.; Bellido, M.J.; Ruiz-de-Clavijo, P.; Baena, C.; Jiménez, C.J.; V 📂 Article 📅 2001 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 394 KB

Fast Monte Carlo Estimation of Timing Yi

Fast Monte Carlo Estimation of Timing Yield With Importance Sampling and Transistor-Level Circuit Simulation

✍ Bayrakci, A.A.; Demir, A.; Tasiran, S. 📂 Article 📅 2010 🏛 IEEE 🌐 English ⚖ 716 KB

[Lecture Notes in Computer Science] Inte

[Lecture Notes in Computer Science] Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation Volume 2451 || Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level

✍ Hochet, Bertrand; Acosta, Antonio J.; Bellido, Manuel J. 📂 Article 📅 2002 🏛 Springer Berlin Heidelberg 🌐 English ⚖ 161 KB

The International Workshop on Power and Timing Modeling, Optimization, and Simulation PATMOS 2002, was the 12th in a series of international workshops 1 previously held in several places in Europe. PATMOS has over the years evolved into a well-established and outstanding series of open European even

[IEEE 2008 IEEE International Symposium

[IEEE 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008 - Seattle, WA, USA (2008.05.18-2008.05.21)] 2008 IEEE International Symposium on Circuits and Systems - Automatic dead-time adjustment CMOS mixed-signal circuit for a DCM-operated 3-level switching power converter

✍ Villar, Gerard; Alarcon, Eduard; Guinjoan, Francesc; Poveda, Alberto 📂 Article 📅 2008 🏛 IEEE ⚖ 264 KB