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Performance and reliability improvements in poly-Si TFT's by fluorine implantation into gate poly-Si

โœ Scribed by Maegawa, S.; Ipposhi, T.; Maeda, S.; Nishimura, H.; Ichiki, T.; Ashida, M.; Tanina, O.; Inoue, Y.; Nishimura, T.; Tsubouchi, N.


Book ID
114536087
Publisher
IEEE
Year
1995
Tongue
English
Weight
698 KB
Volume
42
Category
Article
ISSN
0018-9383

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We have developed low standby power (LSTP) FET utilizing HfSiON dielectric. Due to optimizations of channel and offset spacer structure, we could put threshold voltage of pFET into the place of LSTP region, working through the Fermilevel-pinning effect. This resulted in the reduction of propagation