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Modeling for bridging faults in nMOS combinational circuits

โœ Scribed by Asad A. Ismaeel; Rakesh Bhatnagar; Mohammed Khan


Book ID
108362160
Publisher
Elsevier Science
Year
1997
Tongue
English
Weight
775 KB
Volume
37
Category
Article
ISSN
0026-2714

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Modeling and testing for stuck faults in
โœ Asad A. Ismaeel; Rakesh Bhatnagar ๐Ÿ“‚ Article ๐Ÿ“… 1997 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 968 KB

A transistor level model and a testing methodology are presented for BiCMOS circuits. The model fully describes the functional (logical) grad parametric behavior of the 13iCMOS circuits in the presence of transistor stuck faults. Tile model employs the logic transistor function (LTF). The LTF descri