Mitigating Process Variability and Soft Errors at Circuit-Level for FinFETs

✍ Scribed by Alexandra Zimpeck, Cristina Meinhardt, Laurent Artola, Ricardo Reis

• Publisher: Springer
• Year: 2021
• Tongue: English
• Leaves: 137
• Category: Library

✦ Synopsis

This book evaluates the influence of process variations (e.g. work-function fluctuations) and radiation-induced soft errors in a set of logic cells using FinFET technology, considering the 7nm technological node as a case study. Moreover, for accurate soft error estimation, the authors adopt a radiation event generator tool (MUSCA SEP3), which deals both with layout features and electrical properties of devices. The authors also explore four circuit-level techniques (e.g. transistor reordering, decoupling cells, Schmitt Trigger, and sleep transistor) as alternatives to attenuate the unwanted effects on FinFET logic cells. This book also evaluates the mitigation tendency when different levels of process variation, transistor sizing, and radiation particle characteristics are applied in the design. An overall comparison of all methods addressed by this work is provided allowing to trace a trade-off between the reliability gains and the design penalties of each approach regardingthe area, performance, power consumption, single event transient (SET) pulse width, and SET cross-section.

✦ Table of Contents

Preface
Contents
Acronyms
1 Introduction
1.1 Book Motivation
1.2 Goals
1.3 Outline
References
2 FinFET Technology
2.1 Structure and Properties
2.2 Advancement of Semiconductor Industry
2.3 Layout Design
2.4 Predictive Models
References
3 Reliability Challenges in FinFETs
3.1 Overview
3.2 Process Variability
3.2.1 Sources of Process Variability
Line Edge Roughness
Metal Gate Granularity
Random Dopant Fluctuation
3.2.2 Related Works
3.3 Radiation-Induced Soft Errors
3.3.1 Radiation Effects on Devices
3.3.2 Charge Collection Mechanism
3.3.3 Related Works
References
4 Circuit-Level Mitigation Approaches
4.1 Techniques Overview
4.2 Transistor Reordering
4.3 Decoupling Cells
4.4 Schmitt Trigger
4.5 Sleep Transistors
References
5 Evaluation Methodology
5.1 Design Flow
5.2 Process Variability Evaluation
5.3 Soft Error Estimation
References
6 Process Variability Mitigation
6.1 Device Characterization
6.2 Standard Design
6.3 Transistor Reordering
6.4 Decoupling Cells
6.4.1 Variation Levels Impact
6.4.2 Sizing Influence
6.4.3 Effectiveness of Transistor Reordering
6.5 Schmitt Trigger
6.5.1 Variation Levels Impact
6.5.2 Sizing Influence
6.6 Sleep Transistor
6.6.1 Variation Levels Impact
6.6.2 Sizing Influence
References
7 Soft Error Mitigation
7.1 Standard Design
7.2 Transistor Reordering
7.3 Decoupling Cell
7.4 Schmitt Trigger and Sleep Transistor
References
8 General Trade-Offs
8.1 Technique Drawbacks
8.1.1 Area
8.1.2 Power Consumption
8.1.3 Performance
8.2 Overall Comparison
References
9 Final Remarks
9.1 Relevant Open Research
References
Index