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Low overhead design-for-testability for scan-based delay fault testing

โœ Scribed by YANG, D; CHEN, G; XIE, Y


Book ID
122140003
Publisher
Elsevier Science
Year
2007
Weight
359 KB
Volume
18
Category
Article
ISSN
1004-4132

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Design-for-testability to achieve comple
โœ Irith Pomeranz; Sudhakar M. Reddy ๐Ÿ“‚ Article ๐Ÿ“… 2001 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 207 KB

We propose a testability enhancement technique for delay faults in standard scan circuits that does not involve modiยฎcations to the scan chain. Extra logic is placed on next-state variables, and if necessary, on primary inputs, and can be resynthesized with the circuit to minimize its hardware and p