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[Japan Soc. Applied Phys 2003 Symposium on VLSI Technology. Digest of Technical Papers - Kyoto, Japan (10-12 June 2003)] 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) - Highly stable 65 nm node (CMOS5) 0.56 μm/sup 2/ SRAM cell design for very low operation voltage

✍ Scribed by Kanda, M.; Morifuji, E.; Nishigoori, M.; Fujimoto, Y.; Uematsu, M.; Takahashi, K.; Tsuno, H.; Okano, K.; Matsuda, S.; Oyamatsu, H.; Takahashi, H.; Nagashima, N.; Yamada, S.; Noguchi, T.; Okamoto, Y.; Kakumu, M.

Book ID: 126678465
Publisher: Japan Soc. Applied Phys
Year: 2003
Weight: 190 KB
Category: Article
ISBN-13: 9784891140335
DOI: 10.1109/VLSIT.2003.1221062

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