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[IEEE Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. - Kyoto, Japan (June 14-16, 2005)] Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. - 0.248μm/sup 2/ and 0.334μm/sup 2/ conventional bulk 6T-SRAM bit -cells for 45nm node low cost - general purpose applications

✍ Scribed by Boeuf, F.; Arnaud, F.; Boccaccio, C.; Salvetti, F.; Todeschini, J.; Pain, L.; Jurdit, M.; Manakli, S.; Icard, B.; Planes, N.; Gierczynski, N.; Denorme, S.; Borot, B.; Ortolland, C.; Duriez, B.; Tavel, B.; Gouraud, P.; Broekaart, M.; Dejonghe, V.; Brun, P.; Guyader, F.; Morin, P.; Reddy, C.; Aminpur, M.; Laviron, C.; Smith, S.; Jacquemin, J.P.; Mellier, M.; Andre, F.; Bicais-Lepinay, N.; Jullian, S.; Bustos, J.; Skotnicki, T.

Book ID: 120286011
Publisher: IEEE
Year: 2005
Tongue: Japanese
Weight: 761 KB
Category: Article
ISBN-13: 9784900784000
DOI: 10.1109/.2005.1469240

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