[IEEE Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. - Kyoto, Japan (June 14-16, 2005)] Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005. - Highly cost effective and high performance 65nm S/sup 3/ ( stacked single-crystal Si) SRAM technology with 25f 2 , 0.16μm/sup 2/ cell and doubly stacked SSTFT cell transistors for ultra high density and high speed applications

✍ Scribed by Soon-Moon Jung, ; Rah, Y.; Taehong Ha, ; Hanbyung Park, ; Chulsoon Chang, ; Seungchul Lee, ; Jongho Yun, ; Wonsuk Cho Hoon Lim, ; Jaikyun Park, ; Jaehun Jeong, ; Byoungkeun Son, ; Jaehoon Jang, ; Bonghyun Choi, ; Hoosung Cho, ; Kinam Kim,

• Book ID: 125835357
• Publisher: IEEE
• Year: 2005
• Tongue: Japanese
• Weight: 471 KB
• Category: Article
• ISBN-13: 9784900784000
• DOI: 10.1109/.2005.1469275