[IEEE Comput. Soc IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Yamanashi, Japan (25-27 Oct. 2000)] Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - The effect of placement on yield for standard cell designs

[IEEE Comput. Soc IEEE International Sym

[IEEE Comput. Soc IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Yamanashi, Japan (25-27 Oct. 2000)] Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Path delay fault testability analysis

✍ Sosnowski, J.; Wabia, T.; Bech, T. 📂 Article 📅 2000 🏛 IEEE Comput. Soc ⚖ 657 KB

[IEEE Comput. Soc 1997 IEEE Internationa

[IEEE Comput. Soc 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Paris, France (20-22 Oct. 1997)] 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Multiple fault detection in logic resources of FPGAs

✍ Wei Liang Huang, ; Meyer, F.J.; Lombardi, F. 📂 Article 📅 1997 🏛 IEEE Comput. Soc ⚖ 523 KB

[IEEE Comput. Soc 1997 IEEE Internationa

[IEEE Comput. Soc 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Paris, France (20-22 Oct. 1997)] 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Analysis of defect to yield correlation on memories: method, algorithms and limits

✍ Bichebois, P.; Mathery, P. 📂 Article 📅 1997 🏛 IEEE Comput. Soc ⚖ 568 KB

[IEEE Comput. Soc. Press Proceedings. 19

[IEEE Comput. Soc. Press Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Boston, MA, USA (6-8 Nov. 1996)] Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Trade-offs between yield and reliability enhancement [VLSI]

✍ Venkataraman, A.; Koren, I. 📂 Article 📅 1996 🏛 IEEE Comput. Soc. Press ⚖ 501 KB

[IEEE Comput. Soc. Press Proceedings. 19

[IEEE Comput. Soc. Press Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Boston, MA, USA (6-8 Nov. 1996)] Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Comprehensive modeling of VLSI test

✍ Ziaja, T.; Swartzlander, E. 📂 Article 📅 1996 🏛 IEEE Comput. Soc. Press ⚖ 346 KB

[IEEE Comput. Soc 2001 IEEE Internationa

[IEEE Comput. Soc 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - San Francisco, CA, USA (24-26 Oct. 2001)] Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - A simple via duplication tool for yield enhancement

✍ Harrison, N. 📂 Article 📅 2001 🏛 IEEE Comput. Soc 🌐 English ⚖ 241 KB

Taken from the October 2001 San Francisco conference, 55 papers discuss water scale, yield, dependable design, testing techniques, fault-tolerance in arrays, fault detection, FPGA based applications, fault injection, error correcting codes, mixed signal circuits, defect analysis, self-checking and f