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[IEEE Comput. Soc IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Yamanashi, Japan (25-27 Oct. 2000)] Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Path delay fault testability analysis

✍ Scribed by Sosnowski, J.; Wabia, T.; Bech, T.

Book ID: 126724643
Publisher: IEEE Comput. Soc
Year: 2000
Weight: 657 KB
Category: Article
ISBN-13: 9780769507194
DOI: 10.1109/DFTVS.2000.887174

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