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[IEEE 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) - New York City, NY, USA (2013.10.2-2013.10.4)] 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) - Mixed structural-functional path delay test generation and compaction

✍ Scribed by Bian, Kun; Walker, D. M. H.; Khatri, Sunil P.; Lahiri, Shayak

Book ID: 127261152
Publisher: IEEE
Year: 2013
Weight: 216 KB
Category: Article
ISBN: 1479915831
DOI: 10.1109/dft.2013.6653575

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