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[IEEE 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) - New York City, NY, USA (2013.10.2-2013.10.4)] 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS) - Testing of switch blocks in TSV-reduced Three-Dimensional FPGA

✍ Scribed by Maebashi, Kouta; Namba, Kazuteru; Kitakami, Masato

Book ID: 125513521
Publisher: IEEE
Year: 2013
Weight: 190 KB
Category: Article
ISBN: 1479915831
DOI: 10.1109/DFT.2013.6653623

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