✦ LIBER ✦

High-performance bulk CMOS technology for 65/45 nm nodes

✍ Scribed by T. Sugii

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Advanced front-end processes for the 45&

✍ E.J.H. Collart; S.B. Felch; H. Graoui; D. Kirkwood; S. Tallavarjula; J.A. Van de 📂 Article 📅 2004 🏛 Elsevier Science 🌐 English ⚖ 459 KB

A PVD based barrier technology for the 4

✍ J. Forster; P. Gopalraja; T.J. Gung; A. Sundarrajan; X. Fu; N. Hammond; J. Fu; U 📂 Article 📅 2005 🏛 Elsevier Science 🌐 English ⚖ 318 KB

Design optimization of gate-silicided ES

✍ David Alvarez; Kiran Chatty; Christian Russ; Michel J. Abou-Khalil; Junjun Li; R 📂 Article 📅 2009 🏛 Elsevier Science 🌐 English ⚖ 997 KB

Alternative USJ formation and characteri

✍ John O. Borland 📂 Article 📅 2005 🏛 Elsevier Science 🌐 English ⚖ 336 KB

Temperature scaling for 35 nm gate

✍ Th. Feudel; M. Horstmann; M. Gerhardt; M. Herden; L. Herrmann; D. Gehre; Ch. Kru 📂 Article 📅 2004 🏛 Elsevier Science 🌐 English ⚖ 579 KB

Impact of dummies on interconnects netwo

✍ B. Blampey; B. Fléchet; A. Farcy; M. Gallitre; C. Bermond; O. Cueto; J. Torres; 📂 Article 📅 2006 🏛 Elsevier Science 🌐 English ⚖ 169 KB

High-performance bulk CMOS technology for 65/45&#xa0;nm nodes