✦ LIBER ✦

Electrical and Mechanical Properties of Through-Silicon Vias and Bonding Layers in Stacked Wafers for 3D Integrated Circuits

✍ Scribed by Sung-Hwan Hwang; Byoung-Joon Kim; Ho-Young Lee; Young-Chang Joo

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Electrical modeling and characterization

✍ Ioannis Savidis; Syed M. Alam; Ankur Jain; Scott Pozder; Robert E. Jones; Ritwik 📂 Article 📅 2010 🏛 Elsevier Science 🌐 English ⚖ 541 KB

Processing assessment and adhesion evalu

✍ Y. Yang; R. Labie; F. Ling; C. Zhao; A. Radisic; J. Van Olmen; Y. Travaly; B. Ve 📂 Article 📅 2010 🏛 Elsevier Science 🌐 English ⚖ 677 KB

Wafer-scale 3D integration of InGaAs pho

✍ C.L. Chen; D.-R. Yost; J.M. Knecht; J. Wey; D.C. Chapman; D.C. Oakley; A.M. Soar 📂 Article 📅 2011 🏛 Elsevier Science 🌐 English ⚖ 958 KB

Wafer bonding with nano-imprint resists

✍ Frank Niklaus; Adit Decharat; Fredrik Forsberg; Niclas Roxhed; Martin Lapisa; Mi 📂 Article 📅 2009 🏛 Elsevier Science 🌐 English ⚖ 894 KB

Measurement of stresses in Cu and Si aro

✍ A.S. Budiman; H.-A.-S. Shin; B.-J. Kim; S.-H. Hwang; H.-Y. Son; M.-S. Suh; Q.-H. 📂 Article 📅 2012 🏛 Elsevier Science 🌐 English ⚖ 778 KB