✦ LIBER ✦

Design of Testable CMOS Logic Circuits Under Arbitrary Delays

✍ Scribed by Jha, N.K.; Abraham, J.A.

Book ID: 118698169
Publisher: IEEE
Year: 1985
Tongue: English
Weight: 992 KB
Volume: 4
Category: Article
ISSN: 0278-0070
DOI: 10.1109/tcad.1985.1270122

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Design of Testable Logic Circuits

✍ Taylor, G.E. 📂 Article 📅 1985 🏛 The Institution of Electrical Engineers ⚖ 72 KB

Design of low-power quaternary CMOS logi

Design of low-power quaternary CMOS logic circuits

✍ Chotei Zukeran; Chushin Afuso; Michitaka Kameyama; Tatsuo Higuchi 📂 Article 📅 1986 🏛 John Wiley and Sons 🌐 English ⚖ 641 KB

Design of CMOS multiple–valued logic cir

Design of CMOS multiple–valued logic circuits using only one voltage source

✍ Kazutaka Taniguchi; Fumio Ueno; Takahiro Inoue 📂 Article 📅 1990 🏛 John Wiley and Sons 🌐 English ⚖ 451 KB

On masking of redundant faults in synchr

On masking of redundant faults in synchronous sequential circuits with design-for-testability logic

✍ Pomeranz, I.; Reddy, S.M. 📂 Article 📅 2005 🏛 IEEE 🌐 English ⚖ 338 KB

Design-for-testability to achieve comple

Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits

✍ Irith Pomeranz; Sudhakar M. Reddy 📂 Article 📅 2001 🏛 Elsevier Science 🌐 English ⚖ 207 KB

We propose a testability enhancement technique for delay faults in standard scan circuits that does not involve modi®cations to the scan chain. Extra logic is placed on next-state variables, and if necessary, on primary inputs, and can be resynthesized with the circuit to minimize its hardware and p

Delay Modeling and Statistical Design of

Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation

✍ Datta, A.; Bhunia, S.; Mukhopadhyay, S.; Roy, K. 📂 Article 📅 2006 🏛 IEEE 🌐 English ⚖ 679 KB