Design of low-power quaternary CMOS logic circuits

Design of micropower CMOS quaternary mem

Design of micropower CMOS quaternary memory circuits

✍ Chotei Zukeran; Chushin Afuso; Michitaka Kameyama; Tatsuo Higuchi 📂 Article 📅 1987 🏛 John Wiley and Sons 🌐 English ⚖ 643 KB

High performance low power CMOS dynamic

High performance low power CMOS dynamic logic for arithmetic circuits

✍ Victor Navarro-Botello; Juan A. Montiel-Nelson; Saeid Nooshabadi 📂 Article 📅 2007 🏛 Elsevier Science 🌐 English ⚖ 296 KB

Multi-Voltage CMOS Circuit Design (Kursu

Multi-Voltage CMOS Circuit Design (Kursun/Multi-Voltage CMOS Circuit Design) || Low-Voltage Power Supplies

✍ Kursun, Volkan; Friedman, Eby G. 📂 Article 📅 2006 🏛 John Wiley & Sons, Ltd 🌐 English ⚖ 430 KB

This book presents an in-depth treatment of various power reduction and speed enhancement techniques based on multiple supply and threshold voltages. A detailed discussion of the sources of power consumption in CMOS circuits will be provided whilst focusing primarily on identifying the mechanisms by

Low-power circuit design techniques for

Low-power circuit design techniques for multimedia CMOS VLSIs

✍ Tadahiro Kuroda; Takayasu Sakurai 📂 Article 📅 1998 🏛 John Wiley and Sons 🌐 English ⚖ 233 KB 👁 1 views

Multi-Voltage CMOS Circuit Design (Kursu

Multi-Voltage CMOS Circuit Design (Kursun/Multi-Voltage CMOS Circuit Design) || Sources of Power Consumption in CMOS ICs

✍ Kursun, Volkan; Friedman, Eby G. 📂 Article 📅 2006 🏛 John Wiley & Sons, Ltd 🌐 English ⚖ 662 KB

This book presents an in-depth treatment of various power reduction and speed enhancement techniques based on multiple supply and threshold voltages. A detailed discussion of the sources of power consumption in CMOS circuits will be provided whilst focusing primarily on identifying the mechanisms by

Synthesis of low-power CMOS circuits usi

Synthesis of low-power CMOS circuits using hybrid topologies

✍ Michael Gallant; Dhamin Al-Khalili 📂 Article 📅 1999 🏛 Elsevier Science 🌐 English ⚖ 430 KB

This paper describes the development of a logic synthesis tool, BDDMAP, designed speci"cally to work with a reduced set cell library consisting of a combination of pass logic and standard CMOS topologies. Delay and statistical power models have been developed for pass logic cells to be used in our o