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A sub-10-ns 16×16 multiplier using 0.6-μm CMOS technology

✍ Scribed by Oowaki, Y.; Numata, K.; Tsuchiya, K.; Tsuda, K.; Takato, H.; Takenouchi, N.; Nitayama, A.; Kobayashi, T.; Chiba, M.; Watanabe, S.; Ohuchi, K.; Hojo, A.

Book ID: 119798763
Publisher: IEEE
Year: 1987
Tongue: English
Weight: 1019 KB
Volume: 22
Category: Article
ISSN: 0018-9200
DOI: 10.1109/jssc.1987.1052811

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