A 10 ns 54×54 b parallel structured full array multiplier with 0.5 μm CMOS technology

✍ Scribed by Mori, J.; Nagamatsu, M.; Hirano, M.; Tanaka, S.; Noda, M.; Toyoshima, Y.; Hashimoto, K.; Hayashida, H.; Maeguchi, K.

• Book ID: 119775318
• Publisher: IEEE
• Year: 1991
• Tongue: English
• Weight: 774 KB
• Volume: 26
• Category: Article
• ISSN: 0018-9200
• DOI: 10.1109/4.75061