A back-biased 0.65 μm Leffn CMOS EEPROM technology for next-generation sub 7 ns programmable logic devices

✍ Scribed by Michael J. Hart; Philip J. Cacharelis; Roger D. Carpenter; David G. Tsuei; Raminda U. Madurawe; Bal S. Sandhu; Richard G. Smolen; Andrew P. Dumlao; Tim L. Garverick; Thomas McFarlane; Martin H. Manley

• Book ID: 103598497
• Publisher: Elsevier Science
• Year: 1991
• Tongue: English
• Weight: 240 KB
• Volume: 15
• Category: Article
• ISSN: 0167-9317
• DOI: 10.1016/0167-9317(91)90294-n