✦ LIBER ✦

A simulator for at-speed robust testing of path delay faults in combinational circuits

✍ Scribed by Yuan-Chieh Hsu; Gupta, S.K.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Synthesis of asynchronous circuits for s

✍ Nowick, S.M.; Jha, N.K.; Cheng, F.-C. 📂 Article 📅 1997 🏛 IEEE 🌐 English ⚖ 187 KB

Design-for-testability for path delay fa

✍ Pomeranz, I.; Reddy, S.M. 📂 Article 📅 1998 🏛 IEEE 🌐 English ⚖ 269 KB

Input Necessary Assignments for Testing

✍ Pomeranz, I.; Reddy, S.M. 📂 Article 📅 2011 🏛 IEEE 🌐 English ⚖ 245 KB

A statistical methodology for modeling a

✍ Mustapha Hamad; Sami Al-Arian; David Landis 📂 Article 📅 1997 🏛 Elsevier Science 🌐 English ⚖ 852 KB

A parallel-vector concurrent-fault simul

✍ Gharaybeh, M.A.; Bushnell, M.L.; Agrawal, V.D. 📂 Article 📅 1998 🏛 IEEE 🌐 English ⚖ 140 KB

A Simple Random Test Procedure for Detec

✍ Virupakshia, A.R.; Pratapa Reddy, V.C.V. 📂 Article 📅 1983 🏛 IEEE 🌐 English ⚖ 711 KB