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A 45-ns 64-Mb DRAM with a merged match-line test architecture

✍ Scribed by Mori, S.; Miyamoto, H.; Morooka, Y.; Kikuda, S.; Suwa, M.; Kinoshita, M.; Hachisuka, M.; Arima, H.; Yamada, M.; Yoshihara, T.; Kayano, S.

Book ID: 119776046
Publisher: IEEE
Year: 1991
Tongue: English
Weight: 784 KB
Volume: 26
Category: Article
ISSN: 0018-9200
DOI: 10.1109/4.98962

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