✦ LIBER ✦

A 29-ns 64-Mb DRAM with hierarchical array architecture

✍ Scribed by Nakamura, M.; Takahashi, T.; Akiba, T.; Kitsukawa, G.; Morino, M.; Sekiguchi, T.; Asano, I.; Komatsuzaki, K.; Tadaki, Y.; Songsu Cho; Kajigaya, K.; Tachibana, T.; Sato, K.

Book ID: 119774600
Publisher: IEEE
Year: 1996
Tongue: English
Weight: 896 KB
Volume: 31
Category: Article
ISSN: 0018-9200
DOI: 10.1109/4.535414

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

A 40-ns 64-Mb DRAM with 64-b parallel da

A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture

✍ Taguchi, M.; Tomita, H.; Uchida, T.; Ohnishi, Y.; Sato, K.; Ema, T.; Higashitani 📂 Article 📅 1991 🏛 IEEE 🌐 English ⚖ 653 KB

A 45-ns 64-Mb DRAM with a merged match-l

A 45-ns 64-Mb DRAM with a merged match-line test architecture

✍ Mori, S.; Miyamoto, H.; Morooka, Y.; Kikuda, S.; Suwa, M.; Kinoshita, M.; Hachis 📂 Article 📅 1991 🏛 IEEE 🌐 English ⚖ 784 KB

A 30-ns 256-Mb DRAM with a multidivided

A 30-ns 256-Mb DRAM with a multidivided array structure

✍ Sugibayashi, T.; Takeshima, T.; Naritake, I.; Matano, T.; Takada, H.; Aimoto, Y. 📂 Article 📅 1993 🏛 IEEE 🌐 English ⚖ 760 KB

A 20-ns 4-Mb CMOS SRAM with hierarchical

A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture

✍ Hirose, T.; Kuriyama, H.; Murakami, S.; Yuzuriha, K.; Mukai, T.; Tsutsumi, K.; N 📂 Article 📅 1990 🏛 IEEE 🌐 English ⚖ 595 KB