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A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture

✍ Scribed by Hirose, T.; Kuriyama, H.; Murakami, S.; Yuzuriha, K.; Mukai, T.; Tsutsumi, K.; Nishimura, Y.; Kohno, Y.; Anami, K.

No coin nor oath required. For personal study only.

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