A 15 MIPS 32 b microprocessor: J Yetter, M Forsyth, W Jaffe, D Tanksalvala, J Wheeler (Hewlett Packard, Fort Collins, CO, USA) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First. Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 26–27, 325. In German

A 32 b LISP processor: K Watanabe, A Ish

A 32 b LISP processor: K Watanabe, A Ishikawa, Y Yamada, Y Hibino (Electr. Commun. Labs., NTT, Tokyo, Japan) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp.200–201, 401

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 98 KB

A pipelined 32 b microprocessor with 13

A pipelined 32 b microprocessor with 13 kB of cache memory: A Berenbaum (AT&T Inf. Syst., Holmdel, NJ, USA), B W Colbry, D R Ditzel, R D Freeman, H R McLellan, M Shoji, K J O'Connor 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 34–35, 330. In German

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 98 KB

tained on an 8.4 • 8.4 mm 2 die. The circuit has been designed for an operating frequency of 30 MHz under worst-case conditions. Architectural features include 32-32-b general-purpose registers, 48 or 64-b virtual addressing, and multiprocessor capability, including semaphore instructions and suppor

4 Mb pseudo/virtually SRAM: S Yoshioka,

4 Mb pseudo/virtually SRAM: S Yoshioka, Y Nagatoma, S Takahashi, S Miyamoto, M Uesugi (Oki Electr. Ind. Inc., Tokyo, Japan) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables FL, USA: Lewis Winner, Feb. 1987), pp. 20–21, 320–322. In German

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 91 KB

A 4-K byte/17-ns cache memory has been introduced to a 1.3 pm CMOS/bipolar macrocell library for VLSI computers. The memory includes an address translation function, which uses an MOS memory cell and a comparator merged with a bipolar sense amplifier to accelerate access time. (6 refs.)

A BiCMOS image signal processor with lin

A BiCMOS image signal processor with line memories: Y Kobayashi, T Fukushima, S Miura, M Kanasaki, K Hirasawa (Hitachi Res. Lab., Ibaraki, Japan), K Asada, J Ide, K Yamasaki, Y Tanihara 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 182–183, 392

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 38 KB

A 7 ns 128K multichip ECL RAM-with-logic

A 7 ns 128K multichip ECL RAM-with-logic module: M Iwabuchi, K Ogiue, K Nakamura, S Makagami, S Isomura, S Kuroda, S Kawashima (Hitachi Device Dev. Center, Tokyo, Japan) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 226–227, 411

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 91 KB

A 4-K byte/17-ns cache memory has been introduced to a 1.3 pm CMOS/bipolar macrocell library for VLSI computers. The memory includes an address translation function, which uses an MOS memory cell and a comparator merged with a bipolar sense amplifier to accelerate access time. (6 refs.)

A 120 ns 4 Mb CMOS EPROM: S Atsumi, S Ta

A 120 ns 4 Mb CMOS EPROM: S Atsumi, S Tanaka, S Saito, N Ohtsuka, N Matsukawa, S Mori, Y Kaneko, K Yoshikawa, J Matsunaga, T Iizuka (Toshiba Semicond. Dev. Eng. Lab., Kawasaki, Japan), N ARAI 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 74–75, 344

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 91 KB

A 4-K byte/17-ns cache memory has been introduced to a 1.3 pm CMOS/bipolar macrocell library for VLSI computers. The memory includes an address translation function, which uses an MOS memory cell and a comparator merged with a bipolar sense amplifier to accelerate access time. (6 refs.)

✦ Synopsis