A 7 ns 128K multichip ECL RAM-with-logic module: M Iwabuchi, K Ogiue, K Nakamura, S Makagami, S Isomura, S Kuroda, S Kawashima (Hitachi Device Dev. Center, Tokyo, Japan) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 226–227, 411

A CMOS chip pair for digital TV: S Suzuk

A CMOS chip pair for digital TV: S Suzuki, K Kawai, K Muramatsu, T Makino, S Saji (Toshiba Microelectron. Center, Kawasaki, Japan) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 204–205, 403

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 95 KB

A BiCMOS image signal processor with lin

A BiCMOS image signal processor with line memories: Y Kobayashi, T Fukushima, S Miura, M Kanasaki, K Hirasawa (Hitachi Res. Lab., Ibaraki, Japan), K Asada, J Ide, K Yamasaki, Y Tanihara 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 182–183, 392

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 38 KB

4 Mb pseudo/virtually SRAM: S Yoshioka,

4 Mb pseudo/virtually SRAM: S Yoshioka, Y Nagatoma, S Takahashi, S Miyamoto, M Uesugi (Oki Electr. Ind. Inc., Tokyo, Japan) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables FL, USA: Lewis Winner, Feb. 1987), pp. 20–21, 320–322. In German

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 91 KB

A 4-K byte/17-ns cache memory has been introduced to a 1.3 pm CMOS/bipolar macrocell library for VLSI computers. The memory includes an address translation function, which uses an MOS memory cell and a comparator merged with a bipolar sense amplifier to accelerate access time. (6 refs.)

A 120 ns 4 Mb CMOS EPROM: S Atsumi, S Ta

A 120 ns 4 Mb CMOS EPROM: S Atsumi, S Tanaka, S Saito, N Ohtsuka, N Matsukawa, S Mori, Y Kaneko, K Yoshikawa, J Matsunaga, T Iizuka (Toshiba Semicond. Dev. Eng. Lab., Kawasaki, Japan), N ARAI 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 74–75, 344

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 91 KB

A 4-K byte/17-ns cache memory has been introduced to a 1.3 pm CMOS/bipolar macrocell library for VLSI computers. The memory includes an address translation function, which uses an MOS memory cell and a comparator merged with a bipolar sense amplifier to accelerate access time. (6 refs.)

A 533 K-transistor LISP processor chip:

A 533 K-transistor LISP processor chip: P W Bosshart, C R Hewes, M Chang, K Chau, C Hoac, T W Houston, V Kalyan, S L Lusky, S Mahant-Shetti, D J Matzke, K N Ruparel, C Shaw, T Sridhar, D Stark (Texas Instrum. Inc., Dallas, TX, USA) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, Fl, USA: Lewis Winner, Feb. 1987), pp. 202–203, 402

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 191 KB

A 32 b microprocessor with on-chip 2 K b

A 32 b microprocessor with on-chip 2 K byte instruction cache: M Horowitz, J L Hennessy, P Chow, P G Gulak, J M Acken, A Agarwal, C Chu S A McFarling, S A Przybylski, S Richardson, A Salz, R T Simoni, D C Stark, P Steenkiste, S W K Tjang, M J Wing (Stanford Univ. Center for Integrated Syst., CA, USA) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 30–31, 328. In German

📂 Article 📅 1988 🏛 Elsevier Science 🌐 English ⚖ 98 KB

tained on an 8.4 • 8.4 mm 2 die. The circuit has been designed for an operating frequency of 30 MHz under worst-case conditions. Architectural features include 32-32-b general-purpose registers, 48 or 64-b virtual addressing, and multiprocessor capability, including semaphore instructions and suppor

✦ Synopsis